A watermarking co-processor for new generation graphics processing units

被引:0
|
作者
Mohanty, Saraju P. [1 ]
Pati, Nishikanta [1 ]
Kougianos, Elias [2 ]
机构
[1] Univ N Texas, Denton, TX 76203 USA
[2] Univ N Texas, Elect Engn Technol, Denton, TX 76203 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Recent growth of high speed internet and high resolution imaging has enabled electronic storage and transfer of digital multimedia contents without resorting to the loss of quality. In order to protect the illegal reproduction of the digital multimedia elements, many researchers have suggested digital watermarking as a feasible solution. Like other signal and image processing works, digital watermarking is a computationally intensive process. For efficient, high performance, real time and low cost watermarking we propose two alternatives: (1) Using the Graphics Processing Unit (GPU) available on the modern graphics cards for the complex mathematical computations or (2) Implementing a dedicated processor chip, a coprocessor for the GPU, to accomplish the task. In this paper we present the later alternative, a coprocessor for the GPU to do multimedia watermarking for real-time applications.
引用
收藏
页码:303 / +
页数:2
相关论文
共 50 条
  • [1] A GRAPHICS CO-PROCESSOR AND ITS DISPLAY PROCESSOR ICS
    QUEINNEC, O
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1987, 33 (04) : 551 - 556
  • [2] GRAPHICS CO-PROCESSOR AND ITS DISPLAY PROCESSOR ICS.
    Queinnec, O.
    IEEE Transactions on Consumer Electronics, 1987, CE-33 (04)
  • [3] New decompilation techniques for binary-level co-processor generation
    Stitt, G
    Vahid, F
    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 547 - 554
  • [4] Parallel Data Processing With Magnonic Holographic Co-Processor
    Balynsky, M.
    Gutierrez, D.
    Chiang, H.
    Khitun, A.
    Kozhevnikov, A.
    Khivintsev, Y.
    Dudko, G.
    Filimonov, Y.
    2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC), 2016,
  • [5] Exploring the Vision Processing Unit as Co-processor for Inference
    Rivas-Gomez, Sergio
    Pena, Antonio J.
    Moloney, David
    Laure, Erwin
    Markidis, Stefano
    2018 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW 2018), 2018, : 589 - 598
  • [6] Efficient co-processor utilization in database query processing
    Bress, Sebastian
    Beier, Felix
    Rauhe, Hannes
    Sattler, Kai-Uwe
    Schallehn, Eike
    Saake, Gunter
    INFORMATION SYSTEMS, 2013, 38 (08) : 1084 - 1096
  • [7] A parallel co-processor architecture for block cipher processing
    Yu, Xue-Rong
    Dai, Zi-Bin
    Yang, Xiao-Hui
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 842 - 845
  • [8] Automatic instruction generation for application specific co-processor
    Sang, ST
    Li, XM
    Ye, YZ
    2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 854 - 857
  • [9] The Design of Co-processor for the Image Processing Single Chip System
    Wu Liming
    Liu Junxiu
    Luo Yuling
    ICCIT: 2009 FOURTH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCES AND CONVERGENCE INFORMATION TECHNOLOGY, VOLS 1 AND 2, 2009, : 943 - +
  • [10] A DSP co-processor for the ARM RISC processor
    Walsh, D
    ELECTRONIC ENGINEERING, 1997, 69 (842): : 43 - +