A Study and Design of CMOS H-Tree Clock Distribution Network in System-on-Chip

被引：14
|
作者：
Loo, Wei-Khee [1 ]
Tan, Kok-Siang [1 ]
Teh, Ying-Khai [1 ]
机构：
[1] Multimedia Univ, Fac Engn, Cyberjaya 63100, Malaysia
来源：
2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年
关键词：
Clocks; CMOS digital integrated circuits;
D O I：
10.1109/ASICON.2009.5351254
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A design of a low skew clock distribution network is presented based on the TSMC 0.18 mu m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment pi-model. The clock network designed is able to operate up to maximum clock speed of 1.1GHz for a 1 x 1 mm(2) chip with zero skew.
引用
收藏
页码：411 / 414
页数：4
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