Multiple-Event Direct to Histogram TDC in 65nm FPGA Technology

被引：0

作者：

Dutton, Neale ^{[1
,2
]}

Vergote, Johannes ^{[1
,2
]}

Gnecchi, Salvatore ^{[1
,2
]}

Grant, Lindsay ^{[1
]}

Lee, David ^{[1
]}

Pellegrini, Sara ^{[1
]}

Rae, Bruce ^{[1
]}

Henderson, Robert ^{[2
]}

机构：

[1] ST Microelect Imaging Div, Edinburgh, Midlothian, Scotland

[2] Univ Edinburgh, Edinburgh, Midlothian, Scotland

来源：

2014 10TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2014) | 2014年

关键词：

TIME; SENSOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range.

引用

页数：5

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