A 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization

被引：0

作者：

Hou, Hegang ^{[1
]}

Wang, Zongmin ^{[1
]}

Kong, Ying ^{[1
]}

Peng, Xinmang ^{[1
]}

Guan, Haitao ^{[1
]}

Wang, Jinhao ^{[1
]}

Ren, Yan ^{[1
]}

机构：

[1] Beijing Microelect Technol Inst, Beijing, Peoples R China

来源：

PROCEEDINGS OF THE 2015 JOINT INTERNATIONAL MECHANICAL, ELECTRONIC AND INFORMATION TECHNOLOGY CONFERENCE (JIMET 2015) | 2015年 / 10卷

关键词：

Multi-clock synchronization; quad-switch; digital-to-analog converter;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

timing between the internal digital and analog domains. The quad-switch architecture is also adopted to mask the code-dependent glitches. The full-scale output current can be programmed over the 10mA to 30mA range, and the typical full-scale output current is 20mA. The device is manufactured on a standard 0.18um CMOS process and operates from 1.8V and 3.3V supplies.

引用

页码：939 / 944

页数：6

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