A Hardware Acceleration Scheme for Memory-Efficient Flow Processing

被引：0

作者：

Yang, Xin ^{[1
]}

Sezer, Sakir ^{[1
]}

O'Neill, Shane ^{[1
]}

机构：

[1] Queens Univ Belfast, ECIT Inst, Belfast, Antrim, North Ireland

来源：

2014 27TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2014年

基金：

英国工程与自然科学研究理事会;

关键词：

flow lookup table; content addressable memory; hash; network flow processing; POWER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

引用

页码：437 / 442

页数：6

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