Electrical critical dimension metrology for 100-nm linewidths and below

In this paper, we have demonstrated an electrical CD process capable of resolving linewidths well below 100 nm compatible with a standard polysilicon patterning flow. Appropriate selection of dopant species combined with a reduction in anneal temperature were the primary means for achieving a physical to electrical linewidth bias of 20 nm. These findings supported our hypothesis that dopant out-diffusion was the primary source of the bias. Also, ECD metrology is applied to quantifying poly CD variations in the presence of substrate topography.