Electrical critical dimension metrology for 100-nm linewidths and below

被引：7

作者：

Grenville, A ^{[1
]}

Coombs, B ^{[1
]}

Hutchinson, J ^{[1
]}

Kuhn, K ^{[1
]}

Miller, D ^{[1
]}

Troccolo, P ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

OPTICAL MICROLITHOGRAPHY XIII, PTS 1 AND 2 | 2000年 / 4000卷

关键词：

electrical linewidth metrology; electrical critical dimension metrology; ECD; wafer flatness; wafer topography;

D O I：

10.1117/12.389034

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we have demonstrated an electrical CD process capable of resolving linewidths well below 100 nm compatible with a standard polysilicon patterning flow. Appropriate selection of dopant species combined with a reduction in anneal temperature were the primary means for achieving a physical to electrical linewidth bias of 20 nm. These findings supported our hypothesis that dopant out-diffusion was the primary source of the bias. Also, ECD metrology is applied to quantifying poly CD variations in the presence of substrate topography.

引用

页码：452 / 459

页数：8

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