Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: on Gate Integrity and Device Characteristics

被引：31
|
作者：
Veloso, A. [1 ]
Cho, M. J. [1 ]
Simoen, E. [1 ]
Hellings, G. [1 ]
Matagne, P. [1 ]
Collaert, N. [1 ]
Thean, A. [1 ]
机构：
[1] Imec, Kapeldreef 75, B-3001 Heverlee, Belgium
来源：
DIELECTRICS FOR NANOSYSTEMS 7: MATERIALS SCIENCE, PROCESSING, RELIABILITY, AND MANUFACTURING | 2016年 / 72卷 / 02期
关键词：
LOW-FREQUENCY-NOISE; BORDER TRAPS; BEHAVIOR;
D O I：
10.1149/07202.0085ecst
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
This work reports a comprehensive evaluation of lateral gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, with both types of devices built with various doping schemes, and with GAA-NWFETs outperforming others per footprint. Optimized junctionless (JL) GAA-NWFETs exhibit excellent electrostatics and smaller I-OFF values. They also yield ring oscillators (RO) with substantially lower power dissipation, while showing considerably longer BTI lifetimes. Improved reliability and increased robustness against process variations in the GAA formation module are also obtained for extensionless vs. reference inversion-mode (IM) FETs built with conventional junctions, at comparable device and circuit performance. JL GAA-NWFET devices also show improved on and off state hot carrier (HC) reliability and reduced low frequency (LF) noise, with some of them also exhibiting smaller subthreshold slope (SS) values after HC stress. In addition, further improvements in the noise, reliability and mobility performance of GAA-NWFETs can be obtained by introduction of a TiAl-based EWF-metal in the gate stack.
引用
收藏
页码：85 / 95
页数：11
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