Trans-capacitance modeling in junctionless gate-all-around nanowire FETs

被引：22
|
作者：
Jazaeri, Farzan [1 ]
Barbut, Lucian [1 ]
Sallese, Jean-Michel [1 ]
机构：
[1] Swiss Fed Inst Technol, EPFL, CH-1015 Lausanne, Switzerland
来源：
SOLID-STATE ELECTRONICS | 2014年 / 96卷
基金：
瑞士国家科学基金会;
关键词：
AC analysis; Trans-capacitance; Compact model; Gate-all-around; Nanowire; Junctionless; MOSFETS;
D O I：
10.1016/j.sse.2014.04.022
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this brief, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme recently pointed out between JL NW FET and its double gate counterpart for which such a model has been proposed. This approach is validated by 3D Technology Computer Aided Design simulations and bridges the gap between the nanowire junctionless device and its application in circuits. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码：34 / 37
页数：4
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