Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

被引：0
|
作者：
Yi, Boram [1 ]
Yang, Geun Soo [2 ]
Barraud, Sylvain [3 ]
Bervard, Laurent [3 ]
Lee, Jae Woo [4 ]
Yang, Ji-Woon [4 ]
机构：
[1] Samsung Co, Design Enablement Team, Hwaseong, South Korea
[2] Samsung Co, Semicond R&D Ctr, Hwaseong, South Korea
[3] Univ Grenoble Alpes, CEA LETI, Minatec Campus, Grenoble, France
[4] Korea Univ, Dept Elect & Informat Engn, Sejong, South Korea
来源：
SOLID-STATE ELECTRONICS | 2022年 / 189卷
关键词：
Compact model; Gate-all-around MOSFETs; Low-frequency noise; Nanowire MOSFETs; 1/F NOISE;
D O I：
10.1016/j.sse.2021.108223
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this study, the bias dependence of low-frequency noise (LFN) in nanowire type gate-all-around (GAA) MOSFETs was physically modeled. In the model, the inversion carrier density distribution was considered based on the potential in the channel that changes according to the bias. The developed model was verified with measurement data of the fabricated device. The model could help circuit designers to optimize noise performance in analog/RF applications when designing integrated circuits using nanowire-type GAA MOSFETs.
引用
收藏
页数：4
相关论文
共 50 条
  • [41] Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications
    Yin, Yiheng
    Zhang, Zhaofu
    Zhong, Hongxia
    Shao, Chen
    Wan, Xuhao
    Zhang, Can
    Robertson, John
    Guo, Yuzheng
    ACS APPLIED MATERIALS & INTERFACES, 2021, 13 (02) : 3387 - 3396
  • [42] Transport through Single Dopants in Gate-All-Around Silicon Nanowire MOSFETs (SNWFETs)
    Hong, B. H.
    Jung, Y. C.
    Hwang, S. W.
    Cho, K. H.
    Yeo, K. H.
    Yeoh, Y. Y.
    Suk, S. D.
    Li, M.
    Kim, D. -W.
    Park, D.
    Oh, K. S.
    Lee, W. -S.
    2008 IEEE SILICON NANOELECTRONICS WORKSHOP, 2008, : 51 - +
  • [43] A low-frequency noise model for advanced gate-stack MOSFETs
    Celik-Butler, Zeynep
    Devireddy, Siva Prasad
    Tseng, Hsing-Huang
    Tobin, Philip
    Zlotnicka, Ania
    MICROELECTRONICS RELIABILITY, 2009, 49 (02) : 103 - 112
  • [44] High Aspect Ratio Silicon Nanowire for Stiction Immune Gate-All-Around MOSFETs
    Han, Jin-Woo
    Moon, Dong-Il
    Choi, Yang-Kyu
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (08) : 864 - 866
  • [45] Low temperature single electron characteristics in gate-all-around MOSFETs
    Pott, Vincent
    Bouvet, Didier
    Boucart, Julien
    Tschuor, Lucas
    Moselund, Kirsten E.
    Ionescu, Adrian M.
    ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 427 - +
  • [46] A physics-based low frequency noise model for MOSFETs under periodic large signal excitation
    Brederlow, R
    Koh, J
    Thewes, R
    SOLID-STATE ELECTRONICS, 2006, 50 (04) : 668 - 673
  • [47] A physics-based low frequency noise model for MOSFETs under periodic large signal excitation
    Brederlow, R
    Koh, J
    Thewes, R
    PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 333 - 336
  • [48] Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications
    Yogesh Pratap
    Rajni Gautam
    Subhasis Haldar
    R. S. Gupta
    Mridula Gupta
    Journal of Computational Electronics, 2016, 15 : 492 - 501
  • [49] Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications
    Pratap, Yogesh
    Gautam, Rajni
    Haldar, Subhasis
    Gupta, R. S.
    Gupta, Mridula
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2016, 15 (02) : 492 - 501
  • [50] III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications
    Song, Yi
    Zhang, Chen
    Dowdy, Ryan
    Chabak, Kelson
    Mohseni, Parsian K.
    Choi, Wonsik
    Li, Xiuling
    IEEE ELECTRON DEVICE LETTERS, 2014, 35 (03) : 324 - 326
12345