Analysis of Multifin n-FinFET for Analog Performance at 30nm Gate Length

被引：0
|
作者：
Sonkusare, Reena S. [1 ]
Rathod, S. S. [2 ]
机构：
[1] Sardar Patel Inst Technol, Elect & Telecommun Dept, Bombay, Maharashtra, India
[2] Sardar Patel Inst Technol, Elect Dept, Bombay, Maharashtra, India
来源：
PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES) | 2016年
关键词：
FinFETs; 3-D numerical simulations; Transconductance; Output resistance; Intrinsic gain; Parasitic resistance and capacitance; mobility; Cut-off frequency;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Multi-gate FET, a self-aligned structure (FinFET) is one of the most promising device to address leakage issues and short channel effects in deeply scaled CMOS technology nodes. In order to improve the analog performance of the system the figure of merits (FoMs) of device technology should relate to those of circuit level FoMs. In this paper, based on Visual-TCAD 3-D numerical simulations, we analyze the effect of multi-fin structure and resulting impact of various RF parameters like transconductance, output resistance, intrinsic gain, parasitic resistance and capacitance, mobility, early voltage, drain conductance and cut-off frequency which affects the analog behavior of multi-fin FinFETs device.
引用
收藏
页码：277 / 283
页数：7
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