Analog/RF Performance of Thin (∼10 nm) HfO2 Ferroelectric FDSOI NCFET at 20 nm Gate Length

被引：0
|
作者：
Mehrotra, Shruti [1 ]
Qureshi, Shafi [1 ]
机构：
[1] Indian Inst Technol Kanpur, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India
来源：
2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2018年
关键词：
Analog/RF; HfO2; ferroelectric; Negative capacitance; PGP FDSOI n-MOSFET; PGP FDSOI n-NCFET; Unity short-circuit current gain frequency; NEGATIVE-CAPACITANCE; MOSFET; SOI;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a simulation study of analog/RE performance of PGP FDSOI n-NCFET with a thin (similar to 10 nm) layer of Si doped HfO2 as ferroelectric in the gate stack. A comparison is drawn with the analog/RE performance of the corresponding baseline PGP EDSOI n-MOSFET. The study has been performed at both device level and circuit level. The devices have a metal gate length of 20 nm and the supply voltage is 0.7 V. The f(T) value of FDSOI n-NCFET is seen to be marginally higher than that of the baseline FDSOI n-MOSFET. The frequency response of three basic amplifier topologies, viz., common-source, common gate and source follower using FDSOI n-NCFET have also been discussed in this paper.
引用
收藏
页数：3
相关论文
共 50 条
  • [1] Potential of Thin (∼10 nm) HfO2 Ferroelectric FDSOI NCFET for Performance Enhancement in Digital Circuits at Reduced Power Consumption
    Qureshi, S.
    Mehrotra, Shruti
    2018 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2018, : 225 - 228
  • [2] Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack
    Barral, V.
    Poiroux, T.
    Andrieu, F.
    Buj-Dufournet, C.
    Faynot, O.
    Ernst, T.
    Brevard, L.
    Fenouillet-Beranger, C.
    Lafond, D.
    Hartmann, J. M.
    Vidal, V.
    Allain, F.
    Daval, N.
    Cayrefourcq, I.
    Tosti, L.
    Munteanu, D.
    Autran, J. L.
    Deleonibus, S.
    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 61 - +
  • [3] Improved analog performance of FDSOI based NCFET with a ferroelectric-paraelectric-dielectric gate stack
    Kansal, Harshit
    Medury, Aditya Sankar
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2022, 37 (10)
  • [4] High-κ Dielectrics on 20nm FDSOI FinFET: Study on Analog and RF Performance
    Nikhil, G. P. V. Y.
    Dimri, Chinmay
    Mohanty, P. K.
    Saha, R.
    Routray, S.
    2020 IEEE CALCUTTA CONFERENCE (CALCON), 2020, : 102 - 105
  • [5] Comparative scalability of PVD and CVD TiN on HfO2 as a metal gate stack for FDSOI cMOSFETs down to 25nm gate length and width
    Andrieu, F.
    Faynot, O.
    Garros, X.
    Lafond, D.
    Buj-Dufournet, C.
    Tosti, L.
    Minoret, S.
    Vidal, V.
    Barbe, J. C.
    Allain, F.
    Rouchouze, E.
    Vandroux, L.
    Cosnier, V.
    Casse, M.
    Delaye, V.
    Carabasse, C.
    Burdin, M.
    Rolland, G.
    Guillaumot, B.
    Colonna, J. P.
    Besson, P.
    Brevard, L.
    Mariolle, D.
    Holliger, P.
    Vandooren, A.
    Fenouillet-Beranger, C.
    Martin, F.
    Deleonibus, S.
    2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 382 - +
  • [6] High frequency performance of sub-100 nm UTB-FDSOI featuring TiN/HfO2 gate stack
    Lim, Tao Chuan
    Rozeau, Olivier
    Buj, Christel
    Paccaud, Michel
    Lepilliet, Sylvie
    Dambrine, Gilles
    Danneville, Francois
    SOLID-STATE ELECTRONICS, 2009, 53 (04) : 433 - 437
  • [7] Ferroelectric Gate Field-Effect Transistors with 10nm Thick Nondoped HfO2 Utilizing Pt Gate Electrodes
    Kim, Min Gee
    Kataoka, Masakazu
    Mailig, Rengie Mark D.
    Ohmi, Shun-ichiro
    IEICE TRANSACTIONS ON ELECTRONICS, 2020, E103C (06): : 280 - 285
  • [8] Sub-10-nm ferroelectric Gd-doped HfO2 layers
    Skopin, E., V
    Guillaume, N.
    Alrifai, L.
    Gonon, P.
    Bsiesy, A.
    APPLIED PHYSICS LETTERS, 2022, 120 (17)
  • [9] HF characterisation of sub-100nm UTB-FDSOI with TiN/HfO2 gate stack
    Lim, T. C.
    Rozeau, O.
    Buj, C.
    Paccaud, M.
    Dambrine, G.
    Danneville, F.
    ULIS 2008: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON, 2008, : 145 - +
  • [10] High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond
    Liu, Q.
    Vinet, M.
    Gimbert, J.
    Loubet, N.
    Wacquez, R.
    Grenouillet, L.
    Le Tiec, Y.
    Khakifirooz, A.
    Nagumo, T.
    Cheng, K.
    Kothari, H.
    Chanemougame, D.
    Chafik, F.
    Guillaumet, S.
    Kuss, J.
    Allibert, F.
    Tsutsui, G.
    Li, J.
    Morin, P.
    Mehta, S.
    Johnson, R.
    Edge, L. F.
    Ponoth, S.
    Levin, T.
    Kanakasabapathy, S.
    Haran, B.
    Bu, H.
    Bataillon, J. -L.
    Weber, O.
    Faynot, O.
    Josse, E.
    Haond, M.
    Kleemeier, W.
    Khare, M.
    Skotnicki, T.
    Luning, S.
    Doris, B.
    Celik, M.
    Sampson, R.
    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
12345