An approach to high-level synthesis system validation using formally verified transformations

被引：4

作者：

Radhakrishnan, R ^{[1
]}

Teica, E ^{[1
]}

Vemuri, R ^{[1
]}

机构：

[1] Univ Cincinnati, Dept ECECS, Cincinnati, OH 45221 USA

来源：

IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/HLDVT.2000.889564

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Complexity of advanced high-level synthesis algorithms call be attributed to design quality concerns. However, this complexity may lead to software are errors in their implementations which ma?, adversely impact design correctness. Transformational synthesis is a synthesis methodology where localized, behavior-presenting register transfer level (RTL) transformations are used to obtain a correct and constraint satisfying RTL design. This paper presents the novel we of a set of such transformations ill validating an existing non-transformational synthesis system by discovering and to some extent isolating software errors.

引用

页码：80 / 85

页数：6

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