A novel SOI-LDMOS with field plate auxiliary doping layer that has improved breakdown voltage

被引:5
|
作者
Xiang, Zhenyu [1 ]
Lin, Yonghui [1 ]
Zhang, Chunwei [1 ]
Guo, Haijun [1 ]
Li, Yang [1 ]
Yue, Wenjing [1 ]
Gao, Song [1 ]
Kan, Hao [1 ]
机构
[1] Univ Jinan, Sch Informat Sci & Engn, Jinan 250022, Peoples R China
基金
中国国家自然科学基金;
关键词
Field plate (FP); Lateral double diffused MOS (LDMOS); Silicon on insulator (SOI); Charge balance; Field plate auxiliary doping layer (FPADL); PERFORMANCE;
D O I
10.1016/j.sse.2021.108227
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Field plate (FP) is a widely used electric field optimization technique in lateral power devices. However, we found that the electric field distribution optimized by FP still has poor uniformity due to the excessive induced charges at the end of FP. To solve the problem, a novel silicon on insulator based lateral double diffused metal oxide semiconductor (SOI-LDMOS) with a field plate auxiliary doping layer (FPADL) is proposed. Our investigation proved that the FPADL introduces an additional part of space charge and partially balances the excessive induced charges at the end of FP. As a result, the FPADL introduces an additional electric field peak and improves the electric field distribution. Thereby, the SOI-LDMOS with FPADL has improved breakdown voltage (BV). The effect of FPADL is verified experimentally. In our experiment, the FPADL is realized by modifying the mask of buffer layer to avoid increasing the process cost. The measurement results showed that, comparing with the conventional SOI-LDMOS with FP, the proposed SOI-LDMOS with FPADL improved the BV by 9.52% with the onresistance and the process cost maintained. Therefore, the proposed SOI-LDMOS with FPADL is a promising device.
引用
收藏
页数:7
相关论文
共 50 条
  • [1] An embedded β-Ga2O3 layer in a SOI-LDMOS to improve breakdown voltage
    Farshad Gholipour
    Ali A. Orouji
    Dariush Madadi
    Journal of Computational Electronics, 2022, 21 : 206 - 213
  • [2] An embedded β-Ga2O3 layer in a SOI-LDMOS to improve breakdown voltage
    Gholipour, Farshad
    Orouji, Ali A.
    Madadi, Dariush
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2022, 21 (01) : 206 - 213
  • [3] 3-D effect of cell designs on the breakdown voltage of power SOI-LDMOS
    Suzuki, Y
    Kishida, T
    Takano, H
    Shirai, Y
    Suzumura, M
    1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 134 - 135
  • [4] An improved SOI LDMOS with buried field plate
    Wang, Ying
    Bao, Meng-tian
    Wang, Yi-Fan
    Yu, Cheng-hao
    Cao, Fei
    SUPERLATTICES AND MICROSTRUCTURES, 2017, 111 : 340 - 349
  • [5] The Investigation of a SOI-LDMOS Equipped with the Poly-PiN-diode Field Plate
    Li, Junhong
    Xiao, Kun
    POWER AND ENERGY SYSTEMS ENGINEERING, (CPESE 2017), 2017, 141 : 489 - 493
  • [6] Improving Breakdown Voltage for a Novel SOI LDMOS with a Lateral Variable Doping Profile on the Top Interface of the Buried Oxide Layer
    Jin, Jingjing
    Hu, Shengdong
    Chen, Yinhui
    Tan, Kaizhou
    Luo, Jun
    Zhou, Feng
    Chen, Zongze
    Huang, Ye
    ADVANCES IN CONDENSED MATTER PHYSICS, 2015, 2015
  • [7] Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure
    Jagamohan Sahoo
    Rajat Mahapatra
    Journal of Computational Electronics, 2021, 20 : 1711 - 1720
  • [8] Effect of SOI LDMOS epitaxial layer thickness on breakdown voltage
    Wu, Cheng-Yen
    You, Hsin-Chiang
    2018 INTERNATIONAL SYMPOSIUM ON COMPUTER, CONSUMER AND CONTROL (IS3C 2018), 2018, : 80 - 83
  • [9] Potential floating layer SOI LDMOS for breakdown voltage enhancement
    Zheng, Zhi
    Li, Wei
    Li, Ping
    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 281 - 283
  • [10] Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure
    Sahoo, Jagamohan
    Mahapatra, Rajat
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2021, 20 (05) : 1711 - 1720