Stress Tuning in NanoScale FinFETs at 7nm

被引：0
|
作者：
Dash, T. P. [1 ]
Dey, S. [1 ]
Das, S. [1 ]
Mohaptra, E. [1 ]
Jena, J. [1 ]
Maiti, C. K. [1 ]
机构：
[1] Siksha O Anusandhan Deemed Univ, Dept Elect & Commun Engn, Bhubaneswar 751030, Odisha, India
来源：
PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES KOLKATA CONFERENCE (IEEE EDKCON) | 2018年
关键词：
Strain Engineering; FinFETs; SiGe; Source/drain stressor design; strain tuning TCAD;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.
引用
收藏
页码：166 / 170
页数：5
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