High Speed, Low Power 8T Full Adder Cell with 45% Improvement in Threshold Loss Problem

被引：0

作者：

Sharma, Tripti ^{[1
]}

Singh, B. P. ^{[1
]}

Sharma, K. G. ^{[1
]}

Arora, Neha ^{[1
]}

机构：

[1] MITS Deemed Univ, Elect & Commun Dept, Lakshmangarh, Rajasthan, India

来源：

RECENT ADVANCES IN NETWORKING, VLSI AND SIGNAL PROCESSING | 2010年

关键词：

Full adder; high speed; low power; PDP; XOR gate; VLSI; XOR;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. Demands for the low power VLSI have been pushing the development of design methodologies aggressively to reduce the power consumption drastically. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The present study proposes a low power full adder cell with least MOS transistor count that reduces the serious problem of threshold loss. It considerably increases the speed. Result shows 45% improvement in threshold loss problem and considerable reduction in power consumption over the other types of adders with comparable performance. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm and 130nm technologies.

引用

页码：272 / +

页数：3

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