Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

被引:42
|
作者
Jeon, HeungJun [1 ]
Kim, Yong-Bin [1 ]
Choi, Minsu [2 ]
机构
[1] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA
[2] Missouri Univ Sci & Technol, Dept Elect & Comp Engn, Rolla, MO 65409 USA
基金
美国国家科学基金会;
关键词
Band-to-band tunneling (BTBT) leakage; gate leakage; leakage current; leakage power; optimal body bias voltage; subthreshold leakage; MOSFETS;
D O I
10.1109/TIM.2010.2044710
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (I-SUB) and the band-to-band tunneling (BTBT) current (I-BTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25 degrees C to 100 degrees C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25 degrees C and 100 degrees C, respectively, on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.
引用
收藏
页码:1127 / 1133
页数:7
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