Multiplierless fast Fourier transform architecture

被引：5

作者：

Jiang, M. ^{[1
]}

Yang, B. ^{[1
]}

Huang, R. ^{[1
]}

Zhang, T. Y. ^{[1
]}

Wang, Y. Y. ^{[1
]}

机构：

[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China

来源：

ELECTRONICS LETTERS | 2007年 / 43卷 / 03期

关键词：

D O I：

10.1049/el:20073049

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multiplierless processor architecture is proposed for hardware implementation of fast Fourier transform. Distributed arithmetic is applied to simplify expensive butterfly operations and twiddle multiplications. The novel architecture can largely reduce area cost by replacing complex multipliers and adders with DA lookup tables. Both 8-bit and 16-bit 64-point FFT processors were designed, and the synthesis result shows the designs can attain much lower area cost while keeping real-time processing speed.

引用

页码：191 / 192

页数：2

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