Multiplierless fast Fourier transform architecture

被引：5
|
作者：
Jiang, M. [1 ]
Yang, B. [1 ]
Huang, R. [1 ]
Zhang, T. Y. [1 ]
Wang, Y. Y. [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
ELECTRONICS LETTERS | 2007年 / 43卷 / 03期
关键词：
D O I：
10.1049/el:20073049
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A multiplierless processor architecture is proposed for hardware implementation of fast Fourier transform. Distributed arithmetic is applied to simplify expensive butterfly operations and twiddle multiplications. The novel architecture can largely reduce area cost by replacing complex multipliers and adders with DA lookup tables. Both 8-bit and 16-bit 64-point FFT processors were designed, and the synthesis result shows the designs can attain much lower area cost while keeping real-time processing speed.
引用
收藏
页码：191 / 192
页数：2
相关论文
共 50 条
  • [21] Fourier Analysis and the Fast Fourier Transform
    Salvat-Pujol, Francesc
    OPTICA PURA Y APLICADA, 2008, 41 (01): : 31 - 41
  • [22] MULTIPLIERLESS LIFTING BASED FFT VIA FAST HARTLEY TRANSFORM
    Suzuki, Taizo
    Kyochi, Seisuke
    Tanaka, Yuichi
    Ikehara, Masaaki
    Aso, Hirotomo
    2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2013, : 5603 - 5607
  • [23] A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals
    Garrido, Mario
    Unnikrishnan, Nanda K.
    Parhi, Keshab K.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (11) : 1693 - 1697
  • [24] A Modified Serial Commutator Architecture for Real-Valued Fast Fourier Transform
    Park, Sungjin
    Jeon, Dongsuk
    2020 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 2020, : 170 - 175
  • [25] Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform Architecture Design
    Chao, Hung-Lin
    Peng, Chun-Yang
    Wu, Cheng-Chien
    Huang, Ken-Shin
    Lu, Chun-Hsien
    Shen, Jih-Sheng
    Hsiung, Pao-Ann
    PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2013, : 426 - 429
  • [26] The hazard-free superscalar pipeline fast Fourier transform algorithm and architecture
    Mohd, Bassam Jamil
    Aziz, Adnan
    Swartzlander, Earl E., Jr.
    VLSI-SOC 2007: PROCEEDINGS OF THE 2007 IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, 2007, : 194 - 199
  • [27] A novel pipelined fast Fourier transform architecture for double rate OFDM systems
    Lin, HL
    Lin, H
    Chen, YC
    Chang, RC
    2004 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, PROCEEDINGS, 2004, : 7 - 11
  • [28] Reconfigurable fast Fourier transform architecture for orthogonal frequency division multiplexing systems
    Manolopoulos, KE
    Nakos, KG
    Reisis, DI
    Vlassopoulos, NG
    CCCT 2003, VOL6, PROCEEDINGS: COMPUTER, COMMUNICATION AND CONTROL TECHNOLOGIES: III, 2003, : 24 - 29
  • [29] An Efficient Folded Pipelined Architecture For Fast Fourier Transform Using Cordie Algorithm
    Nizar, Shymna
    Krishna, Abhila R.
    2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 462 - 467
  • [30] A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization
    Kelefouras, Vasilios I.
    Athanasiou, George S.
    Alachiotis, Nikolaos
    Michail, Harris E.
    Kritikakou, Angeliki S.
    Goutis, Costas E.
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2011, 59 (12) : 6217 - 6226
12345