Source/drain optimization of double gate FinFET considering GIDL for low standby power devices

Practical design of double-gate Undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (L-g) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.