Source/drain optimization of double gate FinFET considering GIDL for low standby power devices

被引：2

作者：

Tanaka, Katsuhiko ^{[1
]}

Takeuchi, Kiyoshi ^{[1
]}

Hane, Masami ^{[1
]}

机构：

[1] NEC Corp Ltd, Syst Devices Res Lab, Sagamihara, Kanagawa 2291198, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2007年 / E90C卷 / 04期

关键词：

FinFET; double gate; GIDL; device simulation; LSTP;

D O I：

10.1093/ietele/e90-c.4.842

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Practical design of double-gate Undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (L-g) is equal to 25 nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10 nm fin width.

引用

页码：842 / 847

页数：6

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