Efficient FPGA implementation of bit-stream multipliers

被引：6

作者：

Ng, C. W. ^{[1
]}

Wong, N. ^{[1
]}

Ng, T. S. ^{[1
]}

机构：

[1] Univ Hong Kong, Dept Elect & Elect Engn, Hong Kong, Hong Kong, Peoples R China

来源：

ELECTRONICS LETTERS | 2007年 / 43卷 / 09期

关键词：

D O I：

10.1049/el:20070293

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A four-input adder structure for the FPGA implementation of a sigma-delta bit-stream multiplier is proposed. Conventional bit-stream multiplier implementations involve two-input adder circuits. It is shown that the four-input adder structure is more resource-efficient (over 40% hardware savings) and faster (over 20% higher clock frequency) when implemented using state-of-the-art FPGA architecture featuring six-input look-up tables.

引用

页码：496 / 497

页数：2

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