The Design of Co-processor for the Image Processing Single Chip System

被引：5

作者：

Wu Liming ^{[1
]}

Liu Junxiu ^{[1
]}

Luo Yuling ^{[2
]}

机构：

[1] Guangdong Univ Technol, Fac Informat Engn, Guangzhou 510006, Guangdong, Peoples R China

[2] Guangdong Univ Technol, Fac Automat, Guangzhou 510006, Guangdong, Peoples R China

来源：

ICCIT: 2009 FOURTH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCES AND CONVERGENCE INFORMATION TECHNOLOGY, VOLS 1 AND 2 | 2009年

关键词：

embedded system; image processing; bitonic sort; parallel computing;

D O I：

10.1109/ICCIT.2009.26

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks is evaluated and presented in this paper. The system architecture is based on Field Programmable Gate Array (FPGA) featuring soft-core processor MicroBlaze core processor and an external median filter co-processor using bitonic sort. The FPGA is based on a Xilinx Virtex-II Pro chip and is designed as a system on a programmable chip with the help of Embedded Design Kit. The system integrates the MicroBlaze, external and on chip memory, and median filter appropriate for the evaluation of the system performance. By using the median filter co-processor, the result shows that the process, speed can be accelerated more than 10X. And resources occupied are given.

引用

页码：943 / +

页数：2

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