A Software Controlled Hardware Acceleration Architecture for Image Processing Using an Embedded Development Board

Image processing is a computer technology that has been used in various applications such as biometric authentication, surveillance and social media. It is the process of obtaining information from an image by applying a kernel and performing a convolution. This paper presents an implementation of a image processing system accelerated on a FPGA and controlled from a software interface. Morphological filtering was accelerated using a column parallelization technique to achieve maximum throughput. The system was implemented on an Altera Cyclone IV FPGA and was benchmarked against a software implementation using an Intel N2000 processor. The hardware design achieved a efficiency of 12 times compared to software implementation when processing a 256x256 grayscale image.