Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

被引：1

作者：

Yotsuyanagi, Hiroyuki ^{[1
]}

Yamamoto, Masayuki ^{[1
]}

Hashizume, Masaki ^{[1
]}

机构：

[1] Univ Tokushima, Inst Technol & Sci, Dept Informat Solut, Tokushima 7708506, Japan

来源：

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 2010年 / E93D卷 / 01期

关键词：

BIST-aided scan test; scan chain ordering; test data reduction; compatible flip-flops; test pattern generation;

D O I：

10.1587/transinf.E93.D.10

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work. we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering, the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting, the bits in PRPG partterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.

引用

页码：10 / 16

页数：7

共 50 条

[41] Scan-Controlled Pulse Flip-Flops for Mobile Application Processors
Kim, Min-su
Lee, HyoungWook
Park, Jin-Soo
Kim, Chung-Hee
Kang, Juhyun
Shin, Ken
Kagramanyan, Emil
Jung, Gunok
Cho, Ukrae
Shin, Youngmin
Son, Jae Cheol
2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 769 - 772
[42] A neighbor algorithm of scan flip-flops for increasing delay fault coverage
Peng, XG
Luo, XH
Cheng, SG
ICEMI'99: FOURTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1 AND 2, CONFERENCE PROCEEDINGS, 1999, : 721 - 725
[43] Using weighted scan enable signals to improve test effectiveness of scan-based BIST
Xiang, Dong
Chen, Mingjing
Fujiwara, Hideo
IEEE TRANSACTIONS ON COMPUTERS, 2007, 56 (12) : 1619 - 1628
[44] Scan encoded test pattern generation for BIST
Tsai, KH
Rajski, J
Marek-Sadowska, M
ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 548 - 556
[45] Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability*
Goel, Ashish
Bhunia, Swarup
Mahmoodi, Hamid
Roy, Kaushik
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 665 - 670
[46] Improving testability for partial scan circuits based on partition and coupling of flip-flops
Peng, XG
Ma, JL
ISTM/2001: 4TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1 AND 2, CONFERENCE PROCEEDINGS, 2001, : 1625 - 1628
[47] Test-Mode-Only Scan Attack Using the Boundary Scan Chain
Ali, Sk Subidh
Sinanoglu, Ozgur
Karri, Ramesh
2014 19TH IEEE EUROPEAN TEST SYMPOSIUM (ETS 2014), 2014,
[48] Test pattern decompression using a scan chain
Novák, O
Nosek, J
2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2001, : 110 - 115
[49] On improving test quality of scan-based BIST
Tsai, HC
Cheng, KT
Bhawmik, S
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (08) : 928 - 938
[50] Accumulator based test-per-scan BIST
Karpodinis, P
Kagaris, D
Nikolos, D
10TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS, 2004, : 193 - 198

← 1 2 3 4 5 →