Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

被引：1

作者：

Yotsuyanagi, Hiroyuki ^{[1
]}

Yamamoto, Masayuki ^{[1
]}

Hashizume, Masaki ^{[1
]}

机构：

[1] Univ Tokushima, Inst Technol & Sci, Dept Informat Solut, Tokushima 7708506, Japan

来源：

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 2010年 / E93D卷 / 01期

关键词：

BIST-aided scan test; scan chain ordering; test data reduction; compatible flip-flops; test pattern generation;

D O I：

10.1587/transinf.E93.D.10

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work. we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering, the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting, the bits in PRPG partterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.

引用

页码：10 / 16

页数：7

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