Design of a low power architecture for CABAC encoder in H.264

In this paper, we propose a low power architecture for the implementation of context based adaptive binary arithmetic coding (CABAC) system in H.264. CABAC needs to have the accurate probability estimations for most probable symbol (MIPS) to enhance higher compression ratio. This data compression efficiency can be implicitly achieved by iteratively updating probability models stored in the embedded memory for hardware design. Therefore the design of the memory hierarchy and the suitable architecture is an important issue so that the power consumption can be kept low caused by memory accesses for iteratively executing arithmetic coding operations. To address the low power consideration for designing a CABAC encoder, we propose the architecture by using variable length tag cache memory scheme and pipeline structure. The simulation results show that our proposed architecture can achieve 50% power consumption saving, and throughput can be higher than 200Mbps.