A High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoder

被引：0
|
作者：
Liao, Yuan-Hsin [1 ]
Li, Gwo-Long [1 ]
Chang, Tian-Sheuan [1 ]
机构：
[1] Natl Chiao Tung Univ, Graduated Inst Elect Engn, Hsinchu, Taiwan
来源：
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A high throughput context-based adaptive binary arithmetic coding (CABAC) decoding design with hybrid memory architecture for H.264/AVC is presented in this paper. To accelerate the decoding speed with hardware cost consideration, a new hybrid memory two-symbol parallel decoding technique is proposed. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path of two-symbol binary arithmetic decoding procedure. The proposed architecture is implemented by UMC 90nm technology and experimental results show that our proposal can operate at 264 MHz with 42.37k gate count, and the throughput is 483.1 Mbins/sec, which surpasses previous design with 48.6% hardware cost saving.
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收藏
页码：2007 / 2010
页数：4
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