Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO2 Hybrid Bonding

被引：0

作者：

Honda, Yuki ^{[1
]}

Goto, Masahide ^{[1
]}

Watabe, Toshihisa ^{[1
]}

Nanba, Masakazu ^{[1
]}

Iguchi, Yoshinori ^{[1
]}

Saraya, Takuya ^{[2
]}

Kobayashi, Masaharu ^{[2
]}

Higurashi, Eiji ^{[3
]}

Toshiyoshi, Hiroshi ^{[2
]}

Hiramoto, Toshiro ^{[2
]}

机构：

[1] NHK STRL, Tokyo, Japan

[2] Univ Tokyo, Tokyo, Japan

[3] AIST, Tsukuba, Ibaraki, Japan

来源：

2019 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2019年

关键词：

3D integrated circuits (ICs); CMOS integrated circuits; integrated circuit interconnections; silicon-on-insulator (SOI); wafer bonding; multi wafer stacking;

D O I：

10.1109/S3S46989.2019.9320733

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study demonstrates a triple-stacking process of a silicon-on-insulator (SOI) wafer by repeating (1) the embedment of 5-mu m-diameter gold (Au) electrode sites in a polished silicon oxide (SiO2) surface, (2) Au/SiO2 hybrid bonding with a thin silicon layer in between, and (3) subsequent lost-wafer processes. Inverters prepared on separate SOI wafers are vertically connected through Au electrodes. Feasibility tests are performed by developing triple-stacked ring oscillators (ROs) with 101 stages. The experimental results confirm a successful RO operation and indicate that the developed process is promising for three-dimensional integrated circuits using the multi-wafer stacking technique.

引用

页数：3

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