Evaluation of dual-rail CMOS logic styles for self-timed circuits

被引：0
|
作者：
Sartori, Giovani H. [1 ]
Ribas, Renato P. [1 ]
Reis, Andre I. [2 ]
机构：
[1] Univ Fed Rio Grande do Sul, PGMicro, Av Bento Goncalves 9500, BR-91501970 Porto Alegre, RS, Brazil
[2] Nangate A S, DK-2730 Herlev, Denmark
来源：
24TH NORCHIP CONFERENCE, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/NORCHP.2006.329209
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This work evaluates different CMOS logic families for asynchronous circuit design. The comparison is focused on self-timed circuit using four-phase protocol and dual-rail encoding in functional blocks with completion detection. Seven single-output and three multiple-output logic families were compared through electrical simulations taking into account both 0.13 mu m and 90mn CMOS technologies.
引用
收藏
页码：197 / +
页数：2
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