Single-electron pass-transistor logic with multiple tunnel junctions and its hybrid circuit with MOSFETs

被引：2
|
作者：
Cho, YK [1 ]
Jeong, YH
机构：
[1] ETRI, Basic Res Lab, Taejon, South Korea
[2] POSTECH, Dept Elect & Elect Engn, Pohang, South Korea
来源：
ETRI JOURNAL | 2004年 / 26卷 / 06期
关键词：
multiple-tunnel junction; single-electron transistor; pass-transistor logic; hybrid circuit;
D O I：
10.4218/etrij.04.0204.0022
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters C-g=CT=Cclk=1 aF R(T=)5 MOmega, V-clk=40 mV and V-in =20 m V Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.
引用
收藏
页码：669 / 672
页数：4
相关论文
共 50 条
  • [31] Programmable Logic Arrays in Single-Electron Transistor Technology
    Gerousis, Costa
    Grepiotis, Arthur
    ICSES 2008 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS, CONFERENCE PROCEEDINGS, 2008, : 81 - 84
  • [32] Performance of single-electron transistor logic composed of multi-gate single-electron transistors
    Jeong, MY
    Jeong, YH
    Hwang, SW
    Kim, DM
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1997, 36 (11): : 6706 - 6710
  • [33] Performance of single-electron transistor logic composed of multi-gate single-electron transistors
    Pohang Univ of Science and, Technology, Kyungbuk, Korea, Republic of
    Jpn J Appl Phys Part 1 Regul Pap Short Note Rev Pap, 11 (6706-6710):
  • [34] DESIGN AND SIMULATION OF TWO BITS SINGLE-ELECTRON LOGIC CIRCUIT USING DOUBLE QUANTUM DOT SINGLE ELECTRON TRANSISTOR
    Udhiarto, Arief
    Tamam, Mohammad Ali
    Nuryadi, Ratno
    Hartanto, Djoko
    INTERNATIONAL JOURNAL OF TECHNOLOGY, 2014, 5 (02) : 152 - 158
  • [35] Low-power circuit implementation for partial-product addition using pass-transistor logic
    Law, CF
    Rofail, SS
    Yeo, KS
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1999, 146 (03): : 124 - 129
  • [36] Design Of Low Voltage Flip-flop Based On Complementary Pass-Transistor Adiabatic Logic Circuit
    Bhutada, Dhirajkumar S.
    2016 WORLD CONFERENCE ON FUTURISTIC TRENDS IN RESEARCH AND INNOVATION FOR SOCIAL WELFARE (STARTUP CONCLAVE), 2016,
  • [37] Fabrication of tunnel junctions for direct detector arrays with single-electron transistor readout using electron-beam lithography
    Stevenson, TR
    Hsieh, WT
    Li, MJ
    Rhee, KW
    Schoelkopf, RJ
    Stahle, CM
    Teufel, JD
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2003, 13 (02) : 1139 - 1142
  • [38] Novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
    Wang, BT
    Kuo, JB
    PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 694 - 697
  • [39] Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic
    Kim, DH
    Sung, SK
    Kim, KR
    Lee, JD
    Park, BG
    Choi, BH
    Hwang, SW
    Ahn, D
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (04) : 627 - 635
  • [40] Performance Improvement of Single-Electron Reservoir Computing Circuit with Multiple-Tunnel-Junction Single Electron Oscillator
    Watanabe, Shunya
    Oya, Takahide
    2023 SILICON NANOELECTRONICS WORKSHOP, SNW, 2023, : 35 - 36
12345