A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration

被引：8
|
作者：
Lu, Yong-Ru [1 ,2 ]
Liu, Shen-Iuan [1 ,2 ]
Yang, Yu-Che [3 ]
Kang, Han-Chang [3 ]
Chen, Chih-Lung [3 ]
Chan, Ka-Un [3 ]
Lin, Ying-Hsi [3 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei, Taiwan
[3] Realtek Semicond Corp, Res & Dev Ctr, Hsinchu 30010, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2021年 / 68卷 / 03期
关键词：
Loop bandwidth calibration; phase-locked loop; sub-sampling phase detector; pulse width; slew rate;
D O I：
10.1109/TCSII.2020.3022833
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm(2). The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4 similar to 3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from -71.4% to -18.5% at 3.0GHz.
引用
收藏
页码：873 / 877
页数：5
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