Research of SMO process to improve the imaging capability of lithography system for 28nm node and beyond

被引:0
|
作者
Yu, Haibin [1 ]
Zhang, Yueyu [1 ]
Jiang, Binjie [1 ]
Yu, Shirui [1 ]
Mao, Zhibiao [1 ]
机构
[1] Shanghai Huali Microelect Corp, Shanghai, Peoples R China
来源
2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017) | 2017年
关键词
Integrated Circuit Foundry Manufacturing; Source Mask Optimization (SMO); Resolution Enhancement Technology (RET); Optical Proximity Correction (OPC);
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The source-mask optimization (SMO) solution has become one of the most important branches of Resolution enhancement techniques (RET) to extend the imaging process window with next generation computation lithography, which improve the imaging capability of lithographic systems in the integrated circuit foundry manufacturing. Based on the SMO software RET Selection provided by Mentor Graphics Corporation, we have researched the SMO process to improve the imaging capability of lithographic systems for 28run node and beyond: choosing the key patterns, confirming the process window conditions and so on. In this paper, the parameters PV band, MEEF, NILS and DOF have been used to evaluate the free form illumination sources, and the final illumination source have been verified, which generated by ASML scanner.
引用
收藏
页数:3
相关论文
共 49 条
  • [31] Improvement of Rough Interface Between Barrier/Seed Layer and Porous Ultralow k Film for 28nm Technological Node and Beyond
    Zhou, Ming
    Deng, Hao
    Chao, Zhang Bei
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2016, 29 (01) : 17 - 21
  • [32] Imaging capability of low energy electron beam proximity projection lithography toward the 65/45nm node
    Nakano, H
    Nohdo, S
    Oguni, K
    Motohashi, T
    Yoshizawa, M
    Kitagawa, T
    Moriya, S
    EMERGING LITHOGRAPHIC TECHNOLOGIES VII, PTS 1 AND 2, 2003, 5037 : 611 - 621
  • [33] Development of a Production Worthy Non-selective Slurry W-CMP for Logic Applications at 28nm Technology Node and Beyond
    Hsu, Hsin-Kuo
    Hsieh, Y. H.
    Chen, Y. M.
    Lin, W. C.
    Tsai, T. C.
    Wu, J. Y.
    CHEMICAL MECHANICAL POLISHING 11, 2010, 33 (10): : 91 - 97
  • [34] Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond
    Aubel, Oliver
    Hennesthal, Christian
    Hauschildt, Meike
    Poppe, Jens
    Hahn, Jens
    Boemmels, Juergen
    Nopper, Markus
    Seidel, Robert
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (05)
  • [35] Optimization of lithography process to improve image deformation of contact hole sub-90 nm technology node
    Jun, Sungho
    Kim, Juhyun
    Jeong, Eunsoo
    Yun, Youngje
    Kim, Jeahee
    Kim, Keeho
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXI, PTS 1-3, 2007, 6518
  • [36] Reliability Degradation Impact by Ultra Low-k Dielectrics and Improvement Study for BEOL Process beyond 28nm Technology
    Bai, Fanfei
    Song, Xinghua
    2015 China Semiconductor Technology International Conference, 2015,
  • [37] Imaging capability of low-energy electron-beam - Proximity-projection lithography toward the 70 nm node
    Nakano, H
    Oguni, K
    Nohdo, S
    Koike, K
    Moriya, S
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY IX, 2002, 4754 : 827 - 836
  • [38] Research on Circuit-Level Design of High Performance and Low Power FPGA Interconnect Circuits in 28nm Process
    Pang, Yunbing
    Xu, Jiqing
    Zhang, Yufan
    Tao, Xinxuan
    Wang, Jian
    Yang, Meng
    Lai, Jinmei
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1303 - 1305
  • [39] Developing an integrated imaging system for the 70 nm node using high numerical aperture ArF lithography
    Petersen, JS
    Beach, J
    Gerold, DJ
    Maslow, MJ
    DESIGN, PROCESS INTEGRATION, AND CHARACTERIZATION FOR MICROELECTRONICS, 2002, 4692 : 274 - 287
  • [40] In-field in-design metrology target integration for advanced CD and overlay process control via DoseMapper & High Order Overlay correction for 28nm and beyond logic node
    Ducote, J.
    Bernard-Granger, F.
    Le-Gratiet, B.
    Bouyssou, R.
    Bianchini, R.
    Marin, J. C.
    Baron, M. P.
    Gardet, F.
    Devoivre, T.
    Batail, E.
    Pouly, C.
    Gueze, D.
    Thevenon, L.
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXVII, 2013, 8681