Research on Circuit-Level Design of High Performance and Low Power FPGA Interconnect Circuits in 28nm Process

Since the interconnect resources in FPGA cost more than 70% of the chip area, signal delay and power, it plays a crucial role in the implementation of high performance and lower power FPGA to improve performance and reduce power of the interconnect resources. The area, speed and power of the circuit are mutually constrained. Hence, how to design interconnect circuits with better performance and lower power has been a challenge in FPGA design. On the circuit-level design for FPGA interconnect circuits, this paper proposes topology selection strategy and Multi-V, strategy. The experimental results in 28nm process show that the Decode structure has an optimal DAP (Delay-Power product) when the size of MUX is less than 16, while the 2-level structure has an optimal DAP when the size of MUX is bigger than 16,ancl pass transistors and NMOS in the first stage of the subsequent buffer are replaced by the ultra-low V, transistor (ULVT) and low-V1 transistor (LVT) respectively can reduce the PDP(Power-Delay product) of interconnect circuits by 66.6%. Finally, these two strategies are used to optimize 8 types of interconnect circuits, and simulation results show that all the optimization rates of ADP (Area-Delay-Power product) are over 60%.