Research of SMO process to improve the imaging capability of lithography system for 28nm node and beyond

被引：0
|
作者：
Yu, Haibin [1 ]
Zhang, Yueyu [1 ]
Jiang, Binjie [1 ]
Yu, Shirui [1 ]
Mao, Zhibiao [1 ]
机构：
[1] Shanghai Huali Microelect Corp, Shanghai, Peoples R China
来源：
2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017) | 2017年
关键词：
Integrated Circuit Foundry Manufacturing; Source Mask Optimization (SMO); Resolution Enhancement Technology (RET); Optical Proximity Correction (OPC);
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The source-mask optimization (SMO) solution has become one of the most important branches of Resolution enhancement techniques (RET) to extend the imaging process window with next generation computation lithography, which improve the imaging capability of lithographic systems in the integrated circuit foundry manufacturing. Based on the SMO software RET Selection provided by Mentor Graphics Corporation, we have researched the SMO process to improve the imaging capability of lithographic systems for 28run node and beyond: choosing the key patterns, confirming the process window conditions and so on. In this paper, the parameters PV band, MEEF, NILS and DOF have been used to evaluate the free form illumination sources, and the final illumination source have been verified, which generated by ASML scanner.
引用
收藏
页数：3
相关论文
共 49 条
  • [11] A high-quality spacer oxide formation for 28nm technology node and beyond
    Zhang, Bin
    Xiang, Yanghui
    Deng, Hao
    Guo, Shibi
    Zhang, Beichao
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012), 2012, 44 (01): : 407 - 410
  • [12] Advanced Flip-Chip Package Solution for 28nm Si Node and Beyond
    Liu, C. S.
    Chen, C. S.
    Lee, C. H.
    Tsai, H. Y.
    Pu, H. P.
    Cheng, M. D.
    Kuo, T. H.
    Chen, H. W.
    Wu, C. Y.
    Lii, M. J.
    Yu, Doug C. H.
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 436 - 438
  • [13] THE STUDY OF SHALLOW TRENCH ISOLATION GAP-FILL FOR 28NM NODE AND BEYOND
    Bao, Yu
    Zhou, Xiaoqiang
    Sang, Ningbo
    Lei, Tong
    Shi, Gang
    Yi, Hailan
    Zhong, Bin
    Zhou, Jun
    Li, Fang
    Ding, Yi
    Li, Runling
    Zhou, Haifeng
    Fang, Jingxun
    2015 China Semiconductor Technology International Conference, 2015,
  • [14] SMO for 28-nm logic device and beyond: Impact of source and mask complexity on lithography performance
    Nagahara, Seiji
    Yoshimochi, Kazuyuki
    Yamazaki, Hiroshi
    Takeda, Kazuhiro
    Uchiyama, Takayuki
    Hsu, Stephen
    Li, Zhipan
    Liu, Hua-yu
    Gronlund, Keith
    Kurosawa, Terunobu
    Ye, Jun
    Chen, Luoqi
    Chen, Hong
    Li, Zheng
    Liu, Xiaofeng
    Liu, Wei
    OPTICAL MICROLITHOGRAPHY XXIII, 2010, 7640
  • [15] Backend-of-Line Reliability Improvement Options for 28nm Node Technologies and Beyond
    Aubel, O.
    Hennesthal, C.
    Hauschildt, M.
    Beyer, A.
    Poppe, J.
    Talut, G.
    Gall, M.
    Hahn, J.
    Boemmels, J.
    Nopper, M.
    Seidel, R.
    2011 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND MATERIALS FOR ADVANCED METALLIZATION (IITC/MAM), 2011,
  • [16] Advanced Spectra Ellipsometry Application for Multi-layers SiGe at 28nm Node and Beyond
    Hsuan, Teng-Chun
    Hu, Yi-Cheng
    Hsu, Ming Chih
    Zhan, Dian-Zhen
    Yu, Stan
    Chien, Chin-Cheng
    Chang, Shao-Ju Jason
    Chiu, Sheng-Min Samuel
    Huang, Chien-Jen Eros
    Cheng, Chao-Yu Harvey
    Cheng, Juli
    Raphael, Getin
    Jiang, Zhiming
    Carlos, Ygartua
    Tan, Zhengquan
    Hoobler, Ray
    SEMICONDUCTORS, DIELECTRICS, AND METALS FOR NANOELECTRONICS 11, 2013, 58 (07): : 137 - 144
  • [17] Experiments and Analysis to Characterize Logic State Retention Limitations in 28nm Process Node
    Dasnurkar, Sachin
    Datta, Animesh
    Abu-Rahma, Mohamed
    Hieu Nguyen
    Villafana, Martin
    Rasouli, Hadi
    Tamjidi, Sean
    Cai, Ming
    Sengupta, Samit
    Chidambaram, P. R.
    Thirumala, Raghavan
    Kulkarni, Nikhil
    Seeram, Prasanna
    Bhadri, Prasad
    Patel, Prayag
    Yoon, Sei Seung
    Terzioglu, Esin
    2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,
  • [18] Sub Resolution Assist Feature Study in 28nm Node Poly Lithographic Process
    Mao, Xiaoming
    Yang, Zhengkai
    Guo, Xiaobo
    Gan, Zhifeng
    Liu, Biqiu
    Mao, Zhibiao
    2015 China Semiconductor Technology International Conference, 2015,
  • [19] Detection Sensitivity Improvement on STI Module in 28nm process foundry logic node
    Koronel, Dan
    Soni, Govinda
    Gupta, Vijeet
    Beyer, Mirko
    Guenther, Tobias
    Billasch, Torsten
    Soonekindt, Christophe
    van Oostrum, Robert
    Kirsch, Remo
    2014 25TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2014, : 274 - 277
  • [20] A Complete Process Design Kit Verification Flow and Platform for 28nm Technology and Beyond
    Li, Yanfeng
    Li, Miao
    Wong, Waisum
    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1619 - 1622
12345