THE HYBRID FREQUENCY SYNTHESIZER BASED ON DDS AND TWO-LOOP PLL

被引：0

作者：

Romashov, V. V. ^{[1
]}

Khramov, K. K. ^{[1
]}

Yakimenko, K. A. ^{[1
]}

机构：

[1] Vladimir State Univ, Murom Inst Branch, 23 Orlovskaya Str, Murom 602264, Vladimir Reg, Russia

来源：

2014 24TH INTERNATIONAL CRIMEAN CONFERENCE MICROWAVE & TELECOMMUNICATION TECHNOLOGY (CRIMICO) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Applying the PLL system as a multiplier of direct digital synthesizers (DDS) output frequency in hybrid frequency synthesizers was analyzed in this paper. Increasing of DDS output frequency helps to reduce the division ratio in the feedback loop and, as consequence, decrease the phase noise level. It was proved that the PLL multiplier makes a significant contribution to the phase noise level of the hybrid synthesizer. The comparison of noise performances of the hybrid synthesizer and two-loop PLL system was performed.

引用

页码：294 / 295

页数：2

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