Hybrid DDS-PLL Frequency Synthesizer with Reference Clock Modulation

被引：2

作者：

Sajic, S. ^{[1
]}

Maletic, N. ^{[1
]}

Sunjevaric, M. ^{[2
]}

Todorovic, B. M. ^{[2
]}

机构：

[1] Univ Banja Luka, Fac Elect Engn, Banja Luka, Bosnia & Herceg

[2] Inst Comp Based Syst, RT RK, Novi Sad, Serbia

来源：

FREQUENZ | 2013年 / 67卷 / 7-8期

关键词：

DDS; modulation; PLL; reference clock; synthesizer;

D O I：

10.1515/freq-2012-0114

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A scheme of frequency synthesizer with radio frequency modulation using reference clock is proposed, implemented and tested. The synthesizer is based on direct digital synthesis (DDS) and phase locked loop (PLL). The proposed hybrid scheme offers a new approach in frequency modulation of the DDS output signal by modulating the signal used as a reference clock for DDS. The results of measurement confirm a high performance of the proposed scheme.

引用

页码：233 / 236

页数：4

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