Razor: A tool for post-silicon scan ATPG pattern debug and its application

Generation of ATPG patterns require a gate-level simulation model and associated constraints. If the models and the related constraints used to generate patterns are erroneous, then the patterns will likely fail on Silicon. The process of debugging pattern failures on silicon using manual reason in the absence of automated techniques is very time consuming. Further, techniques used for automated defect diagnosis cannot be directly applied to this problem. In this paper we present techniques for debugging ATPG patterns failing on silicon. An automated tool that implements these techniques and is capable of debugging most common errors found in ATPG models and constraints is presented Results from applying the capability on Intel Pentium-4 processor's ATPG patterns are presented.