Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs

Test-power is an important factor that needs to be managed during Automatic Test Pattern Generation (ATPG), silicon bring-up, and in-system test. The current low-power ATPG techniques involve functional clock-gating approaches during capture as well as software and hardware based adjacent-fill techniques during shift, capture for limiting sequential cell toggling activity to reduce the overall power on Automatic Test Equipment (ATE). However, the current approach over-relies on sequential switching activity without considering associated combinational switching activity which results in an inconsistency between the power estimations during ATPG and actual test power on the ATE. Power simulation sign-off data provides more accurate modeling of design's switching-activity and power characteristics. In this paper, we present a new technique that addresses the mismatch between power estimations during ATPG and actual power on ATE by using power-simulation sign-off data during ATPG which allows generating patterns with a capture power profile that more accurately matches the power consumption during ATE test. This technique results in reduced IR-drop and dramatically improves the yield. In this paper, we also present the silicon data from MediaTek designs showing that lower peak power, lower IR drop, and lower Vmin was achieved using the new comprehensive Power-Aware ATPG.