BTI reliability of advanced gate stacks for Beyond-Silicon devices: challenges and opportunities

被引：0

作者：

Groeseneken, G. ^{[1
,2
]}

Franco, J. ^{[1
]}

Cho, M. ^{[1
]}

Kaczer, B. ^{[1
]}

Toledano-Luque, M. ^{[1
]}

Roussel, Ph. ^{[1
]}

Kauerauf, T. ^{[1
]}

Alian, A. ^{[1
]}

Mitard, J. ^{[1
]}

Arimura, H. ^{[1
]}

Lin, D. ^{[1
]}

Waldron, N. ^{[1
]}

Sioncke, S. ^{[1
]}

Witters, L. ^{[1
]}

Mertens, H. ^{[1
]}

Ragnarsson, L. -A. ^{[1
]}

Heyns, M. ^{[1
]}

Collaert, N. ^{[1
]}

Thean, A. ^{[1
]}

Steegen, A. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, Dept Elect Engn ESAT, Leuven, Belgium

来源：

2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2014年

关键词：

TECHNOLOGY SUPERIOR RELIABILITY;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

引用

页数：4

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