BTI reliability of advanced gate stacks for Beyond-Silicon devices: challenges and opportunities

被引：0

作者：

Groeseneken, G. ^{[1
,2
]}

Franco, J. ^{[1
]}

Cho, M. ^{[1
]}

Kaczer, B. ^{[1
]}

Toledano-Luque, M. ^{[1
]}

Roussel, Ph. ^{[1
]}

Kauerauf, T. ^{[1
]}

Alian, A. ^{[1
]}

Mitard, J. ^{[1
]}

Arimura, H. ^{[1
]}

Lin, D. ^{[1
]}

Waldron, N. ^{[1
]}

Sioncke, S. ^{[1
]}

Witters, L. ^{[1
]}

Mertens, H. ^{[1
]}

Ragnarsson, L. -A. ^{[1
]}

Heyns, M. ^{[1
]}

Collaert, N. ^{[1
]}

Thean, A. ^{[1
]}

Steegen, A. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, Dept Elect Engn ESAT, Leuven, Belgium

来源：

2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2014年

关键词：

TECHNOLOGY SUPERIOR RELIABILITY;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

引用

页数：4

共 50 条

[21] NMOS gate electrode selection process for advanced silicon devices
Misra, V
Heuss, G
Suh, YS
Zhong, HC
Lee, JH
RAPID THERMAL AND OTHER SHORT-TIME PROCESSING TECHNOLOGIES III, PROCEEDINGS, 2002, 2002 (11): : 225 - 234
[22] Integrations and challenges of novel high-k gate stacks in advanced CMOS technology
He, Gang
Zhu, Liqiang
Sun, Zhaoqi
Wan, Qing
Zhang, Lide
PROGRESS IN MATERIALS SCIENCE, 2011, 56 (05) : 475 - 572
[23] Reliability issues in advanced High k/metal gate stacks for 45 nm CMOS applications
Groeseneken, G.
Aoulaiche, M.
De Gendt, S.
Degraeve, R.
Houssa, M.
Kauerauf, T.
Pantisano, L.
ASDAM '06: SIXTH INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES AND MICROSYSTEMS, CONFERENCE PROCEEDINGS, 2006, : 15 - 19
[24] Opportunities and challenges in building silicon products in 65nm and beyond
Spirakis, GS
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 2 - 2
[25] Design for reliability with the advanced integrated circuit (IC) technology: challenges and opportunities
Ji, Zhigang
Chen, Haibao
Li, Xiuyan
SCIENCE CHINA-INFORMATION SCIENCES, 2019, 62 (12)
[26] Design for reliability with the advanced integrated circuit(IC) technology: challenges and opportunities
Zhigang JI
Haibao CHEN
Xiuyan LI
Science China(Information Sciences), 2019, 62 (12) : 242 - 245
[27] Design for reliability with the advanced integrated circuit (IC) technology: challenges and opportunities
Zhigang Ji
Haibao Chen
Xiuyan Li
Science China Information Sciences, 2019, 62
[28] Integration of 2D Materials for Advanced Devices: Challenges and Opportunities
Addou, R.
Wallace, R.
2017 INTERNATIONAL CONFERENCE ON SEMICONDUCTOR TECHNOLOGY FOR ULTRA LARGE SCALE INTEGRATED CIRCUITS AND THIN FILM TRANSISTORS (ULSIC VS. TFT 6), 2017, 79 (01): : 11 - 20
[29] Beyond nanoscale DRAM and flash - Challenges and opportunities for research in emerging memory devices
Tran, LC
2004 IEEE WORKSHOP ON MICROELECTRONIC AND ELECTRON DEVICES, 2004, : 35 - 38
[30] Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks
Zhu, Xinhua
Zhu, Jian-min
Li, Aidong
Liu, Zhiguo
Ming, Naiben
JOURNAL OF MATERIALS SCIENCE & TECHNOLOGY, 2009, 25 (03) : 289 - 313

← 1 2 3 4 5 →