PDN Impedance Modeling of 3D System-in-Package

被引：0

作者：

Oizono, Yoshiaki ^{[1
]}

Nabeshima, Yoshitaka ^{[1
]}

Okumura, Takafumi ^{[1
]}

Sudo, Toshio ^{[1
]}

Sakai, Atsushi ^{[2
]}

Ikeda, Hiroaki ^{[2
]}

机构：

[1] Shibaura Inst Technol, Koto Ku, 3-7-5 Toyosu, Tokyo, Japan

[2] Assoc Super Adv Elect Technol, Chuo Ku, Tokyo, Japan

来源：

2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) | 2011年

关键词：

SILICON; TSV; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Power supply impedance of power distribution network (PDN) for a 3D system-in-package (SiP) has been investigated. The 3D SiP consisted of 3 stacked chips and an organic package substrate. These three chips were a memory chip on the top, Si interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. A large number of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. Next, the 3 stacked chips were assembled on the organic package substrate, whose size was 26 mm by 26 mm. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized. In this paper, the PDN impedances of the memory chip, Si interposer, and the logic chip were calculated respectively, and then the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

引用

页数：4

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