Low Power Full Adder Using 8T Structure

被引：0

作者：

Bazzazi, Amin ^{[1
]}

Mahini, Alireza ^{[1
]}

Jelini, Jelveh ^{[1
]}

机构：

[1] Islamic Azad Univ, Dept Comp Engn, Gorgan Branch, Gorgan, Iran

来源：

INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTIST, IMECS 2012, VOL II | 2012年

关键词：

Full Adder; Low Power; CMOS; Delay;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power and high performance 1-bit full adder cell is proposed. The 8T Full Adder technique has been used for the generation of XOR function. Twelve state-of-theart 1-bit full adders and one proposed full adder are simulated with HSPICE using 0.18 mu m CMOS Technology at 1.8V supply voltage. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout. simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power-Delay-Product (PDP). The power consumption of this adder is 200nw.

引用

页码：1190 / 1194

页数：5

共 50 条

[31] A Novel high-speed low power 9T full adder
Kumar, Sreeja S.
Rakesh, S.
MATERIALS TODAY-PROCEEDINGS, 2020, 24 : 1882 - 1889
[32] A Novel Power Efficient 8T SRAM Cell
Sindwani, Ankush
Saini, Suman
2014 RECENT ADVANCES IN ENGINEERING AND COMPUTATIONAL SCIENCES (RAECS), 2014,
[33] Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL
Kumar, A. Kishore
Somasundareswari, D.
Duraisamy, V.
Pradeepa, T. Shunbaga
VLSI DESIGN, 2013,
[34] Low Power Gate Diffusion Input Full Adder using Floating Body
Park, Geuntae
Kim, Youngmin
18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021), 2021, : 337 - 338
[35] A Novel Low Power Multilpier and Full Adder using Hybrid CMOS Logic
Vani, A. Swetha
Lokesh, M. Ratna
Devi, B. Sowmya
Kushal, A. K. K. V. N. S.
Kumar, Aylapogu Pramod
2017 INTERNATIONAL CONFERENCE OF ELECTRONICS, COMMUNICATION AND AEROSPACE TECHNOLOGY (ICECA), VOL 1, 2017, : 303 - 307
[36] Low Power TG Full Adder Design Using CMOS Nano Technology
Sharma, Anjali
Singh, Richa
Mehra, Rajesh
2012 2ND IEEE INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND GRID COMPUTING (PDGC), 2012, : 210 - 213
[37] A Novel 8T SRAM with Minimized Power and Delay
Naik, Sthrigdhara
Kuwelkar, Sonia
2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2017, : 1498 - 1501
[38] Design Topologies For Low Power Cmos Full Adder
Devadas, M.
Kishore, K. Lal
PROCEEDINGS OF THE 2017 INTERNATIONAL CONFERENCE ON INVENTIVE SYSTEMS AND CONTROL (ICISC 2017), 2017, : 493 - 496
[39] Design and implementation of a low power ternary full adder
Srivastava, A
Venkatapathy, K
VLSI DESIGN, 1996, 4 (01) : 75 - 81
[40] Design of 8T ROM Embedded SRAM using Double Wordline for Low Power High Speed Application
Ramakrishnan, M.
Harirajkumar, J.
2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1, 2016, : 921 - 925

← 1 2 3 4 5 →