Universal masking on logic gate level

被引：17
|
作者：
Golic, JD
Menicocci, R
机构：
[1] Telecom Italia, Telecom Italia Lab, Syst Chip, I-10148 Turin, Italy
[2] Univ Roma La Sapienza, Dipartimento Ingn Elettron, I-00184 Rome, Italy
来源：
ELECTRONICS LETTERS | 2004年 / 40卷 / 09期
关键词：
D O I：
10.1049/el:20040385
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed. The results are important for protecting hardware implementations of crytographic algorithms against side-channel attacks.
引用
收藏
页码：526 / 528
页数：3
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