A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units

被引:13
|
作者
Lyakhov, Pavel [1 ]
Valueva, Maria [1 ]
Valuev, Georgii [1 ]
Nagornov, Nikolai [2 ]
机构
[1] North Caucasus Fed Univ, Dept Math Modeling, Stavropol 355009, Russia
[2] St Petersburg Electrotech Univ LETI, Dept Automat & Control Proc, St Petersburg 197376, Russia
来源
APPLIED SCIENCES-BASEL | 2020年 / 10卷 / 24期
关键词
digital signal processing; digital filter; multiply-accumulate unit;
D O I
10.3390/app10249052
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
This paper proposes new digital filter architecture based on a modified multiply-accumulate (MAC) unit architecture called truncated MAC (TMAC), with the aim of increasing the performance of digital filtering. This paper provides a theoretical analysis of the proposed TMAC units and their hardware simulation. Theoretical analysis demonstrated that replacing conventional MAC units with modified TMAC units, as the basis for the implementation of digital filters, can theoretically reduce the filtering time by 29.86%. Hardware simulation showed that TMAC units increased the performance of digital filters by up to 10.89% compared to digital filters using conventional MAC units, but were associated with increased hardware costs. The results of this research can be used in the theory of digital signal processing to solve practical problems such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.
引用
收藏
页码:1 / 11
页数:11
相关论文
共 50 条
  • [31] An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations
    Wang, Yin
    Tang, Hongwei
    Xie, Yufeng
    Chen, Xinyu
    Ma, Shunli
    Sun, Zhengzong
    Sun, Qingqing
    Chen, Lin
    Zhu, Hao
    Wan, Jing
    Xu, Zihan
    Zhang, David Wei
    Zhou, Peng
    Bao, Wenzhong
    NATURE COMMUNICATIONS, 2021, 12 (01)
  • [32] A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process
    Tung, Che-Wei
    Huang, Shih-Hsu
    IEEE ACCESS, 2020, 8 : 87367 - 87377
  • [33] BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator
    Harsh Chhajed
    Gopal Raut
    Narendra Dhakad
    Sudheer Vishwakarma
    Santosh Kumar Vishvakarma
    Circuits, Systems, and Signal Processing, 2022, 41 : 2045 - 2060
  • [34] A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers
    Pari, Britto J.
    Mariammal, K.
    Vaithiyanathan, D.
    WORLD JOURNAL OF ENGINEERING, 2024, 21 (01) : 16 - 30
  • [35] BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator
    Chhajed, Harsh
    Raut, Gopal
    Dhakad, Narendra
    Vishwakarma, Sudheer
    Vishvakarma, Santosh Kumar
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2022, 41 (04) : 2045 - 2060
  • [36] A High Performance Multiply-Accumulate Unit with Double Carry-Save Scheme for 6-Input LUT Based Reconfigurable Systems
    Cini, Ugur
    Kurt, Olcay
    2015 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONICS ENGINEERING (ELECO), 2015, : 940 - 944
  • [37] An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing
    Zhang, Xinyue
    Song, Jiahao
    Wang, Yuan
    Zhang, Yawen
    Zhang, Zuodong
    Wang, Runsheng
    Huang, Ru
    2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [38] FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit
    Cho, Mannhee
    Kim, Youngmin
    ELECTRONICS, 2021, 10 (22)
  • [39] FPGA-Based Implementation of Comb Filters Using Sequential Multiply-Accumulate Operations for Use in Binaural Hearing Aids
    Kambalimath, Shankarayya G.
    Pandey, Prem C.
    Kulkarni, Pandurangarao N.
    Mahant-Shetti, Shivaling S.
    Hiremath, Sangamesh G.
    2014 Annual IEEE India Conference (INDICON), 2014,
  • [40] Power optimized high level synthesis of Multiply-and-accumulate (MAC) based digital filter architectures under SNR constraints
    Manga, N. Alivelu
    Latha, M. Madhavi
    2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,