On Probability of Detection Lossless Concurrent Error Detection Based on Implications

被引:9
|
作者
Wang, Chih-Hao [1 ]
Hsieh, Tong-Yu [1 ]
机构
[1] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 804, Taiwan
关键词
Concurrent error detection (CED); implication reduction; implications; probability of error detection (P-detection); reliability; SCHEME; LEVEL;
D O I
10.1109/TCAD.2017.2740289
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, a new concurrent error detection method by using invariant relationships inside a circuit, called implications, has been proposed. Algorithms have also been developed to reduce the total number of required implications so as to minimize the incurred area overhead due to implication checking logic. This implication reduction process, however, would result in degradation on the probability of error detection (P-detection) of the method. In this paper, we analyze the impact of this issue mathematically together with illustration by a real case study. Our analytical results show that just one percent degradation on P-detection would result in millions more errors being undetected per second and thereby significant loss on reliability of the target circuit. To address this issue, we develop a new implication reduction algorithm that guarantees no loss on Pdetection. In our algorithm, the detectability of errors for each candidate implication is carefully evaluated. The evaluation results are then utilized to select the most efficient candidates for detecting all the detectable errors. We also analyze the computation and memory complexity of the proposed algorithm. The experimental results on 28 representative benchmark circuits from ISCAS'85, ISCAS'89, and ITC'99 show that the implication reduction rate of our method (92.59%) is close to that of the previous work (95.8%). Only a small number of additional implications need to be selected to guarantee no loss on P-detection.
引用
收藏
页码:1090 / 1103
页数:14
相关论文
共 50 条
  • [21] Concurrent Error Detection Adder Based On Two Paths Output Computation
    Khedhiri, Chiraz
    Karmani, Mouna
    Hamdi, Belgacem
    Man, Ka Lok
    2011 NINTH IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS WORKSHOPS (ISPAW), 2011, : 27 - 32
  • [22] Fault analysis for networks with concurrent error detection
    Bolchini, C
    Salice, F
    Sciuto, D
    IEEE DESIGN & TEST OF COMPUTERS, 1998, 15 (04): : 66 - 74
  • [23] Which concurrent error detection scheme to choose?
    Mitra, S
    McCluskey, EJ
    INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 985 - 994
  • [24] Concurrent error detection schemes for involution ciphers
    Joshi, N
    Wu, KJ
    Karri, R
    CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2004, PROCEEDINGS, 2004, 3156 : 400 - 412
  • [25] An IDDQ sensor for concurrent timing error detection
    Knight, CG
    Singh, AD
    Nelson, VP
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (10) : 1545 - 1550
  • [26] RELIABILITY ANALYSIS OF SYSTEMS WITH CONCURRENT ERROR DETECTION
    RAMAMOORTHY, CV
    HAN, YW
    IEEE TRANSACTIONS ON COMPUTERS, 1975, 24 (09) : 868 - 878
  • [27] Concurrent error detection scheme for FCT networks
    Chen, He
    Mao, Zhigang
    Ye, Yizheng
    Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 1999, 36 (10): : 1246 - 1252
  • [28] Concurrent error detection in wavelet lifting transforms
    Redinbo, GR
    Nguyen, C
    IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (10) : 1291 - 1302
  • [29] Concurrent error detection in Reed Solomon decoders
    Cardarilli, G. C.
    Pontarelli, S.
    Re, M.
    Salsano, A.
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 1451 - +
  • [30] On concurrent error detection with bounded latency in FSMs
    Almukhaizim, S
    Drineas, P
    Makris, Y
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 596 - 601