Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization

被引：0

作者：

Li, Yan ^{[1
]}

Schneider, Helmut ^{[2
]}

Schnabel, Florian ^{[2
]}

Thewes, Roland ^{[2
]}

Schmitt-Landsiedel, Doris ^{[1
]}

机构：

[1] Tech Univ Munich, Theresienstr 90, D-82110 Munich, Germany

[2] Qimonda AG, ADCC, PD DLD, D-85579 Neubiberg, Germany

来源：

INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2009年 / 5349卷

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.

引用

页码：126 / +

页数：2

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