Design and Measurement of a Compact On-interposer Passive Equalizer for Chip-to-chip High-speed Differential Signaling

被引：0
|
作者：
Kim, Heegon [1 ]
Cho, Jonghyun [1 ]
Jung, Daniel H. [1 ]
Kim, Jonghoon J. [1 ]
Choi, Sumin [1 ]
Kim, Joungho [1 ]
Lee, Junho [2 ]
Park, Kunwoo [2 ]
机构：
[1] Korea Adv Inst Sci & Technol, TERA Lab, Taejon 305701, South Korea
[2] Hynix Semicond Inc, Adv Design Team, Ichon, South Korea
来源：
2013 9TH INTERNATIONAL WORKSHOP ON ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2013) | 2013年
关键词：
Inter-symbol Interference (ISI); On-interposer passive equalizer; Silicon-interposer; Differential data transmission;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling was proposed and experimentally verified. By using the parasitic resistance and inductance of the coil-shaped on-interposer metal line, the proposed on-interposer passive equalizer achieves not only the wide-band equalization but also the compact size. Moreover, the symmetric structure of the proposed equalizer maintains the balance between the differential signals. The remarkable performance of the proposed on-interposer passive equalizer for differential signaling was successfully verified by a frequency- and time-domain measurement of up to 10 Gbps.
引用
收藏
页码：5 / 9
页数：5
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