Vertical III-V Nanowire Transistors and CMOS Circuits on Si

被引：0
|
作者：
Svensson, Johannes [1 ]
Dey, Anil [1 ]
Jacobsson, Daniel [1 ]
Wernersson, Lars-Erik [1 ]
机构：
[1] Lund Univ, S-22100 Lund, Sweden
来源：
2016 COMPOUND SEMICONDUCTOR WEEK (CSW) INCLUDES 28TH INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE & RELATED MATERIALS (IPRM) & 43RD INTERNATIONAL SYMPOSIUM ON COMPOUND SEMICONDUCTORS (ISCS) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页数：1
相关论文
共 50 条
  • [31] Phonon exacerbated quantum interference effects in III-V nanowire transistors
    Gilbert, M. J.
    Banerjee, S. K.
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2007, 6 (1-3) : 141 - 144
  • [32] III-V nanowire heterostructures
    Dubrovskii, V. G.
    2018 INTERNATIONAL CONFERENCE LASER OPTICS (ICLO 2018), 2018, : 436 - 436
  • [33] Si/III-V CMOS photonics for low-power electronic-photonic integrated circuits on Si platform
    Takenaka, Mitsuru
    Takagi, Shinichi
    2016 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), 2016,
  • [34] A High Performance Vertical Si Nanowire CMOS for Ultra High Density Circuits
    Maheshwaram, Satish
    Kaushal, Gaurav
    Manhas, S. K.
    PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 1219 - 1222
  • [35] III-V compound semiconductor transistors-from planar to nanowire structures
    Riel, Heike
    Wernersson, Lars-Erik
    Hong, Minghwei
    del Alamo, Jesus A.
    MRS BULLETIN, 2014, 39 (08) : 668 - 677
  • [36] Computationally Efficient Analytic Charge Model for III-V Cylindrical Nanowire Transistors
    Ganeriwala, Mohit D.
    Marin, Enrique G.
    Ruiz, Francisco G.
    Mohapatra, Nihar R.
    2018 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2018, : 193 - 195
  • [37] Electrical performance of III-V gate-all-around nanowire transistors
    Razavi, Pedram
    Fagas, Giorgos
    APPLIED PHYSICS LETTERS, 2013, 103 (06)
  • [38] Threshold Tuning of III-V Nanowire Transistors via Metal Clusters Decoration
    Han, N.
    Wang, F. Y.
    Hou, J. J.
    Yip, S. P.
    Lin, H.
    Xiu, F.
    Fang, M.
    Yang, Z. X.
    Hung, T. F.
    Ho, J. C.
    STATE-OF-THE-ART PROGRAM ON COMPOUND SEMICONDUCTORS (SOTAPOCS) 55 -AND- LOW-DIMENSIONAL NANOSCALE ELECTRONIC AND PHOTONIC DEVICES 6, 2013, 58 (08): : 113 - 118
  • [39] A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors
    Ganeriwala, Mohit D.
    Ruiz, Francisco G.
    Marin, Enrique G.
    Mohapatra, Nihar R.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (01) : 73 - 79
  • [40] High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm
    Kilpi, Olli-Pekka
    Hellenbrand, Markus
    Svensson, Johannes
    Persson, Axel R.
    Wallenberg, Reine
    Lind, Erik
    Wernersson, Lars-Erik
    IEEE ELECTRON DEVICE LETTERS, 2020, 41 (08) : 1161 - 1164
12345