Fast DSP Implementation of a Low Complexity LDPC Decoder

被引：0
|
作者：
Razi, Mouhcine [1 ]
Benhayoun, Mhammed [1 ]
Mansouri, Anas [1 ]
Madi, Abdessalam Ait [1 ]
Ahaitouf, Ali [1 ]
机构：
[1] USMBA Univ, ERSI Lab, Fes, Morocco
来源：
2019 INTERNATIONAL CONFERENCE ON WIRELESS TECHNOLOGIES, EMBEDDED AND INTELLIGENT SYSTEMS (WITS) | 2019年
关键词：
LDPC decoders; Min Sum Algorithm; Horizontal Shuffled Scheduling; DSP implementation;
D O I：
10.1109/wits.2019.8723838
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Belief Propagation (BP) algorithm is known as the most efficient algorithm in terms of convergence speed. But this algorithm has a very high level of computational complexity. The MM Sum Algorithm (MSA) permits to reduce this computational complexity but with some performances degradations. In this paper we recommend a new approach with more simplified algorithm, that allows to get performances near to these of the BP algorithm by adopting a new version of the MSA algorithm. This last uses Horizontal Shuffled (HS) scheduling instead of the usually used flooding scheduling. This algorithm was successfully implemented on the Digital Signal Processor (DSP). The results obtained after implementation show that the proposed version of the MSA algorithm does not only improve the decoding performance but also decreases the number of iterations necessary for the decoding of the LDPC codes.
引用
收藏
页数：5
相关论文
共 50 条
  • [11] Design and Implementation of Scalable Throughput Fast Convergence LDPC Decoder
    Sayed, Mostafa A.
    Liu Rongke
    Zhao Ling
    PROCEEDINGS OF 2016 IEEE ADVANCED INFORMATION MANAGEMENT, COMMUNICATES, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (IMCEC 2016), 2016, : 517 - 522
  • [12] Fast implementation of the MPEG-4 AAC main and low complexity decoder
    Servetti, A
    Rinotti, A
    De Martin, JC
    2004 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL V, PROCEEDINGS: DESIGN AND IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS INDUSTRY TECHNOLOGY TRACKS MACHINE LEARNING FOR SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING SIGNAL PROCESSING FOR EDUCATION, 2004, : 249 - 252
  • [13] Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder
    Spagnol, C
    Marnane, W
    Popovici, E
    Proceedings of the 2005 European Conference on Circuit Theory and Design, Vol 1, 2005, : 289 - 292
  • [14] Low Complexity DVB-S2 LDPC Decoder
    Zhang, Botao
    Liu, Hengzhu
    Chen, Xucan
    Liu, Dongpei
    Yi, Xiaofei
    2009 IEEE VEHICULAR TECHNOLOGY CONFERENCE, VOLS 1-5, 2009, : 1609 - 1613
  • [15] A Low-complexity LDPC Decoder Architecture for WiMAX Applications
    Wang, Yu-Luen
    Ueng, Yeong-Luh
    Peng, Chian-Lien
    Yang, Chung-Jay
    2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 294 - 297
  • [16] A Low-complexity LDPC Decoder for NAND Flash Applications
    Li, Mao-Ruei
    Chou, Hsueh-Chih
    Ueng, Yeong-Luh
    Chen, Yun
    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 213 - 216
  • [17] Implementation of a flexible LDPC decoder
    Masera, Guido
    Quaglio, Federico
    Vacca, Fabrizio
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (06) : 542 - 546
  • [18] Design and Implementation of Low Bit Error Rate of LDPC Decoder
    Kshirsagar, Ashlesha P.
    Kakde, Sandeep
    Chawhan, Manish
    Suryawanshi, Yogesh
    2015 FIFTH INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT2015), 2015, : 381 - 384
  • [19] Fpga implementation of a LDPC decoder using a reduced complexity message passing algorithm
    Chandrasetty V.A.
    Aziz S.M.
    Journal of Networks, 2011, 6 (01) : 36 - 45
  • [20] Low-Complexity LDPC Decoder for 5G URLLC
    Liu, Jian-Cheng
    Wang, Huan-Chun
    Shen, Chung-An
    Lee, Jih-Wei
    CONFERENCE PROCEEDINGS OF 2018 IEEE ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIMEASIA 2018), 2018, : 43 - 46
12345